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INTEGRATED CIRCUITS
74ABT544 Octal latched transceiver with dual enable, inverting (3-State)
Product data Supersedes data of 1993 Jun 01 2002 Nov 18
Philips Semiconductors
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
FEATURES
* Combines 74ABT640 and 74ABT373 type functions in one device * 8-bit octal transceiver with D-type latch * Back-to-back registers for storage * Separate controls for data flow in each direction * Output capability: +64 mA/-32 mA * Live insertion/extraction permitted * Power-up 3-State * Power-up reset * Latch-up protection exceeds 500 mA per JEDEC Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
The 74ABT544 Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64 mA.
FUNCTIONAL DESCRIPTION
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (LEAB) input are LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and invert the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
DESCRIPTION
The 74ABT544 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25 C; GND = 0 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC Outputs disabled; VO = 0 V or VCC Outputs disabled; VCC = 5.5 V TYPICAL 3.9 4 7 110 UNIT ns pF pF A
ORDERING INFORMATION
TYPE NUMBER 74ABT544N 74ABT544D 74ABT544DB 74ABT544PW PACKAGE DIP24: 24-pin plastic dual in-line package SO24: 24-pin plastic small outline package SSOP24: 24-pin plastic shrink small outline package; Type II TSSOP24: 24-pin thin shrink small outline package; Type I TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
LEBA OEBA 1 2 24 VCC 23 EBA 22 B0 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 LEAB 13 OEAB
PIN DESCRIPTION
PIN NUMBER 14, 1 11, 23 13, 2 3, 4, 5, 6, 7, 8, 9, 10 22, 21, 20, 19, 18, 17, 16, 15 12 24 SYMBOL LEAB / LEBA EAB / EBA OEAB / OEBA A0 - A7 B0 - B7 GND VCC FUNCTION A-to-B / B-to-A Latch Enable input (active-LOW) A-to-B / B-to-A Enable input (active-LOW) A-to-B / B-to-A Output Enable input (active-LOW) Port A, 3-State outputs Port B, 3-State outputs Ground (0 V) Positive supply voltage
A0 3 A1 4 A2 A3 5 6
A4 7 A5 8 A6 9
A7 10 EAB 11 GND 12
SA00168
2002 Nov 18
2
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
2 23 1 13 3 4 5 6 7 8 9 10 11 14 1EN3 (AB) G1 1C5 2EN4 (BA) G2 2C6 22 5D 4 21 20 19 18 17 16 15
A0 A1 A2 A3 A4 A5 A6 A7 11 23 14 1 EAB EBA LEAB LEBA B0 B1 B2 B3 B4 B5 B6 B7 OEAB OEBA 13 2
3 4
3 5D
5 6 7 8
22 21 20 19 18 17 16 15
9 10
SA00169
SA00183
FUNCTION TABLE
INPUTS OEXX H X L L L L L L H= h= L= l= X= = NC= Z= EXX X H L L L L LEXX X X L L L L An or Bn X X h l h l H L OUTPUTS An or Bn Z Z Z Z L H L H Disabled Disabled Disabled + Latch Latch + Display Transparent Hold STATUS
L L H X NC High voltage level High voltage level one set-up time prior to the LOW-to-HIGH clock transition Low voltage level Low voltage level one set-up time prior to the LOW-to-HIGH clock transition Don't care LOW-to-HIGH clock transition No change High impedance or "OFF" state
2002 Nov 18
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Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
LOGIC DIAGRAM
DETAIL A D LE Q 22 B0
A0
3 Q D LE
A1 A2 A3 A4 A5 A6 A7
4 5 6 7 8 9 10 DETAIL A x 7
21 20 19 18 17 16 15
B1 B2 B3 B4 B5 B6 B7
OEBA
2 13
OEAB
EBA
23 11
LEBA
1
EAB
14
LEAB
SA00184
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Storage temperature range VO < 0 V output in OFF or HIGH state output in LOW state VI < 0 V CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Nov 18
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Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range PARAMETER Min 4.5 0 2.0 - - - 0 -40 LIMITS Max 5.5 VCC - 0.8 -32 64 10 +85 V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 C Min VIK Input clamp voltage VCC = 4.5 V; IIK = -18 mA VCC = 4.5 V; IOH = -3 mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0 V; IOH = -3 mA; VI = VIL or VIH VCC = 4.5 V; IOH = -32 mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output low voltage3 In ut Input leakage current Control pins Data pins VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = GND or 5.5 V VCC = 5.5 V; VI = GND or 5.5 V VCC = 0.0 V; VI or VO 4.5 V VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; VOE = Don't care VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; Outputs HIGH; VI = GND or VCC Quiescent supply current VCC = 5.5 V; Outputs LOW; VI = GND or VCC VCC = 5.5 V; Outputs 3-State; VI = GND or VCC Additional supply current per input pin2 VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND; VCC = 5.5 V - 2.5 3.0 2.0 - - - - - - - - - -50 - - - - Typ -0.9 3.2 3.7 2.3 0.42 0.13 0.01 5 5.0 5.0 5.0 -5.0 5.0 -65 110 20 110 0.3 Max -1.2 - - - 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40 C to +85 C Min - 2.5 3.0 2.0 - - - - - - - - - -50 - - - - Max -1.2 - - - 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 V V V V V V A A A A A A A mA A mA A mA UNIT
IOFF IPU/PD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC
Power-off leakage current Power-up/down 3-State output current4 3-State output HIGH current 3-State output LOW current Output HIGH leakage current Output current1
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition of 10 msec. From VCC = 2.1 V to VCC = 5V 10%, a transition time of up to 100 sec is permitted.
2002 Nov 18
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Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
AC CHARACTERISTICS
GND = 0 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation delay An to Bn, Bn to An Propagation delay LEBA to An, LEAB to Bn Output enable time OEBA to An, OEAB to Bn Output disable time OEBA to An, OEAB to Bn Output enable time EBA to An, EAB to Bn Output disable time EBA to An, EAB to Bn 1 1, 2 4 5 4 5 4 5 4 5 1.1 1.4 1.6 2.1 1.4 2.5 2.5 1.0 1.4 2.5 2.5 1.0 Tamb = +25 C VCC = +5.0 V Typ 3.6 3.9 4.1 4.6 3.9 5.0 5.9 5.5 3.9 5.0 5.9 5.5 Max 5.1 5.4 5.6 6.1 5.4 6.5 7.4 7.0 5.4 6.5 7.4 7.0 Tamb = -40 C to +85 C VCC = +5.0 V 0.5 V Min 1.1 1.4 1.6 2.1 1.4 2.5 3.4 3.0 1.4 2.5 3.4 3.0 Max 6.1 6.4 6.6 7.1 6.4 7.5 8.4 8.0 6.4 7.5 8.4 8.0 ns ns ns ns ns ns UNIT
AC SET-UP REQUIREMENTS
GND = 0 V; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(L) Set-up time An to LEAB, Bn to LEBA Hold time An to LEAB, Bn to LEBA Set-up time An to EAB, Bn to EBA Hold time An to EAB, Bn to EBA Latch Enable pulse width, LOW 3 3 3 3 3 3.0 3.0 0.5 0.5 3.0 3.0 0.5 0.5 3.5 Tamb = +25 C VCC = +5.0 V Typ 1.5 0.6 -0.3 -1.3 1.5 0.6 -0.2 -1.3 1.8 Tamb = -40 C to +85 C VCC = +5.0 V 0.5 V Min 3.0 3.0 0.5 0.5 3.0 3.0 0.5 0.5 3.5 ns ns ns ns ns UNIT
2002 Nov 18
6
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
AC WAVEFORMS
VM = 1.5 V; VIN = GND to 3.0 V
OEAB, OEBA, EAB, EBA
VIN
VM tPHL
VM tPLH
VM tPZH
VM tPHZ VOH VOH -0.3V 0V
VOUT
VM
VM
An, Bn
VM
SA00172
SA00175
Waveform 1. Propagation delay for inverting output
Waveform 4. 3-State Output Enable time to HIGH level and Output Disable time from HIGH level
VIN
VM tPLH
VM tPHL
OEAB, OEBA, EAB, EBA
VM tPZL
VM tPLZ
VOUT
VM
VM
An, Bn
VM
VOL +0.3V 0V
SA00173
SA00176
Waveform 2. Propagation delay for non-inverting output
Waveform 5. 3-State Output Enable time to LOW level and Output Disable time from LOW level
An, Bn
LEAB, LEBA
NOTE: For all waveforms, VM = 1.5V, the shaded areas indicate when the input is permitted to change for predictable output performance. SA00174
2002 Nov 18
EEEEEEEEE EEE E EEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) VM tw(L) VM
Waveform 3. Data set-up and hold times and Latch Enable pulse width
7
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
TEST CIRCUIT AND WAVEFORM
VCC 7.0 V VIN PULSE GENERATOR RT D.U.T. CL RL POSITIVE PULSE 10% tW VOUT RL 90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90% VM 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW 90% VM AMP (V)
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5 V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0 V Rep. Rate 1 MHz tW tR tF 2.5 ns
500 ns 2.5 ns
2002 Nov 18
8
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
2002 Nov 18
9
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
2002 Nov 18
10
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
2002 Nov 18
11
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
2002 Nov 18
12
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
REVISION HISTORY
Rev _2 Date 20021118 Description Product data; second version (9397 750 10752). Supersedes data of 1993 Jun 01. Engineering Change Notice 853-1610 29205 (date: 20021115). 19930601 Product data; initial version. Engineering Change Notice 853-1610 09907 (date: 19930601).
2002 Nov 18
13
Philips Semiconductors
Product data
Octal latched transceiver with dual enable, inverting (3-State)
74ABT544
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 11-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10752
Philips Semiconductors
2002 Nov 18 14

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